1. Technical Field
Embodiments of the present disclosure relate to semiconductor devices having a three dimensional structure and semiconductor systems including the same.
2. Related Art
Recently, three dimensional semiconductor devices have been fabricated to increase the integration density thereof. The three dimensional semiconductor devices may include a plurality of semiconductor chips which are stacked. The plurality of semiconductor chips may be electrically connected to each other by through silicon vias (TSVs) that vertically penetrate the plurality of semiconductor chips. The semiconductor chips included in each three dimensional semiconductor device may receive address signals, command signals, and other signals for entering a test mode and executing a test operation through the TSVs, and the semiconductor chips may output signals and/or data that include some pieces of information. The plurality of semiconductor chips included in each three dimensional semiconductor device may transmit signals to each other through the TSVs. In such a case, lengths of signal paths between the semiconductor device and a controller for controlling the semiconductor device may be reduced to prevent degrading of a signal transmission speed between the semiconductor device and the controller.
After the three dimensional semiconductor devices are fabricated, the three dimensional semiconductor devices have to be tested to confirm whether the three dimensional semiconductor devices operate normally. When a semiconductor device has a plurality of stacked semiconductor chips, it may be important to reduce the test time of the plurality of stacked semiconductor chips without degrading the test reliability. This is because the test time affects the fabrication cost of the semiconductor device. Thus, a lot of effort has been focused on developing a method of reducing the test time of the three dimensional semiconductor devices including TSVs without degrading test reliability.